Half-Day Tutorial: Modern Methods and Languages for High Level Design and Verification (Alan Fitch, Doulos)

The aim of this half-day tutorial is to give attendees a thorough overview of modern design and verification languages and methodologies.

Introduction to High Level Design and Verification
Verification has become one of the biggest issues when designing large and complex System-On-Chip (SoC) designs. Many techniques have been developed to help with verification, either by increasing the level of abstraction of verification environments, or by using more advanced techniques than plain "simulation with vectors".

This introduction will give an overview of verification approaches (such as constrained random verification, formal methods, assertions and virtual prototyping), and the modern languages in which these approaches may be implemented (SystemVerilog, SystemC, Property Specification Language (PSL), VHDL-2008).

Design Methodology
Traditional hardware design has also been evolving recently - in particular in the case where there is a mixture of hardware and software. SoC designs typically have a large number of re-used blocks (which standards such as IP-XACT and TLM2 are addressing) combined with a need to integrate software as soon as possible (through some form of Virtual Prototyping). This part of the tutorial will give an overview of these techniques. It will also look briefly at high level synthesis.

Verification Methodology
To make the subject of verification methodology more concrete, an example of verification of a VHDL RTL design using SystemVerilog and PSL, using coverage-driven verification will be shown.


Information from Doulos on their background and instructor


DOULOS Presentation

Doulos is the global leader for the development and delivery of market leading training solutions for SoC, FPGA and ASIC design and verification. Our business ethos is 'service through excellence' which, when combined with our world-leading independent know-how, makes Doulos the ideal training partner. Our commercial independence and industry wide partnerships enable Doulos to bring significant added value to our clients. This also enables Doulos to make a unique contribution to the EDA industry as a whole in the area of new design and verification methodologies.

Together with our certified and strategic partners across the world we deliver training programs addressing hardware design and verification, processor architectures, embedded software design, and system level modeling.

The Doulos training porfolio includes Embedded C/C++ and Linux, UML, RTOS, VHDL and Verilog, SystemC, SystemVerilog, PSL,Perl and Tcl/Tk. Also Doulos works closely with strategic partners like ARM, Altera and Xilinx to ensure customers benefit from fully integrated training solutions.

Public courses run regularly across Europe and the USA. In-house and team-based training is delivered world-wide, and comes with a guarantee of expert technical interaction to ensure training is precisely tailored to match your requirements.

Doulos course materials are recognised as the best in the industry. No other training provider can match the combination of in-depth technical expertise, training experience, and professional course design encapsulated in our materials. They add value to Doulos training that is difficult to emulate, and provide delegates with comprehensive reference material.

Doulos consultants are technical experts in their field, drawn from right across the industry. But it takes more than technical know-how to become a Doulos tutor. Effective course design and training delivery are skills we take very seriously. And that's why our expert tutors really know how to teach, and are passionate about transferring their know-how. Doulos tutors make learning easier and faster in the context of real world design and verification issues.


Instructor biography

Alan Fitch has a BSc. (Hons) degree in Electronic Engineering, and started his career at Philips Semiconductors (now NXP) working on digital filtering for cellular radio; followed by work on many other topics from digital design using VHDL to specification of Zero-IF radio receivers for digital telephony.

After a brief spell teaching at a further education college in the UK, he joined the global language and methodology training company Doulos in 1998. At Doulos he has continued his involvement in ASIC and FPGA design and modeling through consultancy work, but has also been greatly involved in developing and delivering HDL-related training classes in languages such as VHDL, SystemC, SystemVerilog, PSL, and Verilog. He has a particular specialization in SystemC and VHDL.

Quote from Doulos

This tutorial is sponsored by ACEOLE, a Marie Curie Action at CERN, funded by the European Commission under the 7th Framework Programme.